Design-Reuse

Functional Verification Basics: UVM Tutorial

UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, ...
Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Semiconductor Engineering

Extending UVM To Analog

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...
Design-Reuse

Synopsys Unveils Next-Generation Verification IP for Faster SoC Verification

Synopsys Discovery VIP speeds and simplifies verification of the most complex system-on-chip (SoC) designs. Synopsys Discovery VIP offers greater performance, debug and coverage management features, ...
elEconomista

DVCon Europe "Must See": Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

The 90-minute tutorial focuses on the use of Easier UVM and SCE-MI to help teams get started with UVM and, importantly, to future-proof their UVM verification environments by making them ...