EDN

The case for logic BIST

Chip Design Engineers are on a binge today, drawing up design plans for unprecedented, ever-increasing functionality on a single chip. Many times this surge encounters a brick wall in the form of ...
Semiconductor Engineering

How To Meet Functional Safety Requirements With Built-In-Self-Test

With the rapid growth in semiconductor content in today’s vehicles, IC designers need to improve their process of meeting functional safety requirements defined by the ISO 26262 standard. The ISO ...
Semiconductor Engineering

Improve Logic Test With A Hybrid ATPG/BIST Solution

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a ...
Design-Reuse

BIST versus ATPG -- separating myths from reality

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...
Electronic Design

What’s The Difference Between ATPG And Logic BIST?

Two test strategies are used to test virtually all IC logic: automatic test pattern generation (ATPG) with test pattern compression and logic built-in self-test (BIST). This article will describe how ...
Design-Reuse

The case for logic BIST

Chip Design Engineers are on a binge today, drawing up design plans for unprecedented, ever-increasing functionality on a single chip. Many times this surge encounters a brick wall in the form of ...
EDN

BIST versus ATPG — separating myths from reality

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...